This invention relates to a programmable logic device architecture which integrates fast logic array blocks into a fast central routing scheme. The invention also combines the low cost and speed of dedicated global control input signals with the programming flexibility of control input signals generated locally at each logic array block.
In the past, when a programmable logic device (PLD) architecture employed fast building blocks, significant routing delays were encountered. Shorter and more uniform delays could be achieved, but the price was the use of slower building blocks.
PLDs have also employed logic array block (LAB) architectures which use one of two schemes for providing control input signals (i.e., clocks, presets, clears, output enables) to the individual logic modules or macrocells of which each LAB is comprised. One scheme uses control input signals which are generated locally at each LAB through the use of multiplexing schemes, product-terms, or other combinatorial logic devices. The other uses dedicated global control input signal lines which are routed directly to each macrocell within a LAB.
Generating control input signals locally at the LAB level provides the user with a great deal of programming flexibility. However, such schemes can be costly, slow, and often result in inefficient use of die area due to the inevitable redundancies in device resources. Global dedication of macrocell control input signals, on the other hand, is inexpensive, minimizes redundancies, and exhibits faster clock-to-output delay times than locally generated clock signals. The disadvantage of dedicated global lines is the loss of programming flexibility.
Traditionally, LAB architectures have employed a plurality of logic modules, also known as macrocells, each of which can be programmed to perform complex, multi-variable logic functions. Macrocells have been implemented using programmable look-up tables or product terms. A macrocell employing look-up tables offers advantages in speed, density, programming flexibility, and manufacturing ease. Such macrocells can be programmed to implement specific logic functions by programming the static random access memory (SRAM) architecture bits of its programmable look-up table. A macrocell can be designed with as many logic inputs as required by the logic operations. Complex logic operations tend to require a high number of input variables. Thus, increasing the fan-in of a macrocell enhances its logic capability.
However, a linear increase in the fan-in of a look-up table results in a geometric increase in the number of programmable architecture bits required to implement the look-up table. For example, a 4-input programmable look-up table requires 16 (2.sup.4) programmable architecture bits to implement any 4-variable logic function. An 8-input programmable look-up table requires 256 (2.sup.8) programmable architecture bits to implement any 8-variable logic function.
From the manufacturing perspective, a greater number of programmable architecture bits per macrocell means higher circuit density and lower chip yield. In practical terms, this circuit density constraint places an upper limit on the number of programmable architecture bits and consequently the look-up table fan-in. Thus, while designers have always searched for ways to increase the logic capability of PLDs, the challenge has been to balance the macrocell fan-in against this circuit density constraint.
One method of increasing the logic capability of PLDs while keeping circuit density within acceptable levels involves cascading macrocells. Cascading macrocells facilitates logic operations which require a higher fan-in than is available at any one macrocell. For example, two 4-input macrocells can be cascaded to handle certain logic operations involving eight input variables.
It is recognized, however, that cascading macrocells results in inefficient use of circuitry in a PLD. For example, each macrocell contains, in addition to the look-up table, additional circuitry to control functions such as output, carry-chain, etc. When a macrocell is cascaded, that entire macrocell becomes unavailable for other uses within the PLD even though only the look-up table portion is used. Thus, in a PLD of limited physical size having a finite number of macrocells, a high incidence of cascading is undesirable.
From the foregoing, it can be appreciated that there is a need for a PLD architecture which employs fast building blocks without the routing delays usually experienced in such architectures. There is also a need for an architecture which can be adapted to employ dedicated global control input signals as well as generate local control input signals at the LAB and macrocell levels.
It can also be appreciated from the foregoing that there exists a need for a macrocell design based on programmable look-up tables which can more advantageously increase macrocell fan-in without suffering the geometric increase in the number of programmable architecture bits. Such a high fan-in macrocell could reduce the incidence of cascading for complex logic operations while keeping circuit density within manageable levels.